Cache control system

ABSTRACT

A cache memory unit that preferentially stores specific lines into the cache memory, according to the program nature, dynamically changes the priority ranks of lines, and increases the cache memory hit rate, in which: the lines to be accessed by a processor are divided into groups and definitions of the groups are set in a group definition table; policy whereby to store lines belonging to the groups into the cache memory is set in a policy table; and storing lines into the cache memory is executed, according to the group definitions and the policy of storing set in the above tables.

TECHNICAL FIELD

[0001] The present invention relates to a cache memory unit, placedbetween processors and a main memory, for short-time storage to retainpart of the contents of the main memory, particularly to the cachememory unit that is so designed that specific lines are preferentiallystored into the cache.

DESCRIPTION OF RELATED ART

[0002] A cache is a faster-access memory of small capacity placedbetween a main memory and a processor that executes instructions readfrom the main memory. The cache is to temporarily retain the data ingiven units that the processor fetched or retrieved through the accessto the main memory. Units of data to be stored into the cache are calledblocks or cache lines. In the present Specification, the above units aresimply referred to as lines.

[0003] The processor first accesses the cache to retrieve a line itneeds. If the line exists on the cache (this result is called a hit),the processor uses it; otherwise, the processor accesses the mainmemory. The higher the cache hit rate, more efficient processing can beperformed. To increase the cache hit rate, it is necessary that linesmore frequently accessed remain stored on the cache.

[0004] Analysis of patterns in which programs access the memory showsgeneral tendency: spatial locality that addresses near the accessedaddress are likely to be accessed before long; and temporal localitythat the accessed address is likely to be accessed again before long. Atypical known cache is designed to operate efficiently for programshaving the above tendency. For such cache, data access is performed inline units and data around the required data is stored together with therequired data into the cache. Furthermore, in such cache using the LRU(Least Recently Used) method, a line that has been least recentlyaccessed is replaced by a new line and recently accessed lines are hardto be replaced.

[0005] However, the locality differs for different programs or differentparts of a program. Data access in line units and line replacement bythe LRU method do not always lead to the increase of the cache hit rate.This tendency is noticeable especially for business applicationprograms.

[0006] Cause of the above problem is storing all lines equally into thecache. With the aim of solving this problem, some approaches have beendisclosed that address this problem by preferential storing of specificlines into the cache, which contributes to the enhancement of cacheperformance. These approaches will be mentioned below.

[0007] In an approach described in U.S. Pat. No. 5,546,449 (thisapproach is hereinafter referred to as publicly-known approach example1), a specified line is inhibited from being replaced by another line.

[0008] In an approach described in Japanese Patent Laid-Open PublicationNo. 07-028706 (this approach is hereinafter referred to aspublicly-known approach example 2), priority ranks are assigned to lineswhen the lines are stored into the cache and a line of higher priorityrank is inhibited from being replaced by a line of lower priority rank.

[0009] In an approach described in IA-64 Application Developer'sArchitecture Guide, Intel, May (1999) pp. 4-20 to pp. 4-23 (thisapproach is hereinafter referred to as publicly-known approach example3), hint information is included in an instruction issued from aprocessor and cache operation is controlled to store the line accessedby the instruction into a location of what level in cache hierarchy,based on this information.

[0010] In an approach described in U.S. Pat. No. 5,787,490 (thisapproach is hereinafter referred to as publicly-known approach example4), every process is given a priority rank of the right to use the cacheand the cache operation is controlled, based on this process-specificpriority.

[0011] The above publicly-known approach examples 1, 2, and 3 are, so tosay, the methods in which different cache priority ranks are assigned todifferent lines. However, dynamic change to the way of giving thepriority ranks to the lines is not taken into consideration.

[0012] On the other hand, as for the above publicly-known approachexample 4, it can be said that the priority is changed dynamically.However, the priority that can be changed in this example depends on theprocess for which a line is used.

[0013] Even in a same application, it is conceivable that priority to begiven to an individual line dynamically changes, depending on the loadand use condition. Unless the cache executes line replacement controladaptive to the dynamic change of priority on a line-by-line basis, atpresent, there is a possibility of occurrence of undesirable linereplacement; i.e., a line to preferentially remain stored on the cacheis replaced by a lower priority line, which results in that the totalcache hit rate cannot be increased sufficiently.

SUMMARY OF THE INVENTION

[0014] Accordingly, an object of the present invention is to offer acache that enables dynamic priority change on a per line basis so thatthe cache will preferentially retain higher priority lines and the cachehit rate will be increased, and enables more efficient memory access.

[0015] Another object of the invention is to offer a cache memory unitapplicable to an information processing system in which computerresources can be divided into a plurality of partitions and differentapplications are run in different partitions, the cache enabling theuser to specify lines to be handled preferentially and an optimum method(policy) whereby to store grouped lines into the cache per partition.

[0016] Another object of the invention is to offer a cache memory unitthat achieves a higher cache hit rate than a typical known cache thathandles lines equally, which can be configured simply by modifying thesystem.

[0017] In the cache memory system configured, according to a typicalembodiment mode of the invention, grouping method for dividing linesinto some groups is set into a table. Also, storing policy for storinglines into the cache memory is defined as to each of groups set into thetable. When an access command issued from a processor to access the mainmemory is turn out to be a miss hit on the cache memory, the objectiveline is read from the main memory and line attribute of the objectiveline, to which group the objective line belongs, in other words, isdetermined according to the table. Then, the objective line is storedinto the cache memory according to control information of the cachememory and a storing policy of the corresponding group.

[0018] Detailed configuration of the above cache memory system is asfollows. The cache memory unit comprises a cache memory comprising aplurality of entries, each of which consists of data area where to storea line and control information are where to store control informationfor the line, a group definition controller that is used to divide linesthat may be read by the processor from the main memory into some groupsand specify definitions of the groups, a group selector to determine oneof the groups to which the line belongs in accordance with the groupdefinitions and the information in a command issued from the processorto read data from the main storage, a policy definition controller thatis used to assign policy of storing whereby to store lines belonging thegroups into the cache memory, and a storing means to read a line fromthe main memory and store the line into the cache memory in accordancewith the group to which the line belongs, the line control informationretained in the cache memory for the candidates lines to be replaced,and the policy of storing if a read request from the processor resultsin a missed hit.

[0019] In the foregoing publicly-known approach examples, 1, 2, and 3,when a line is stored into the cache, if it is stored in accordance withthe priority rank assigned to it at this point, this storing mannerappears to be adaptive to dynamic priority change. In the case of thepublicly-known approach examples 1 and 2, however, the priority rank ofa line is recorded as control information into the cache memory when theline is stored into the cache. If, for example, a line L1 has priorityP1 when it is stored into the cache, the priority P1 information isrecorded into the cache memory together with the line L1 as the line L1is stored. Even if the priority P1 of the line L1 is updated to lowerpriority P1′ later, the cache memory retains the priority P1 informationfor the line L1I as is. Suppose that a new line L2 having priority L2and the same index as the line L1 is stored into the cache and thepriority ranking is P1′<P2<P1. At the point of storing the line L2, thepriority P2 of the line L2 is higher than the priority P1′ of the lineL1, and thus the line L1 should be replaced by the line L2. Inactuality, the line L2 is, however, not stored into the cache becausethe comparison is made between the old priority information P1 for theline L1, recorded in the cache, and the priority P2 of the line L2, andthe priority of the L1 is judged higher than that of the L2.

[0020] In the case of the publicly-known approach example 3, threelevels of cache hierarchy are set: level 1 cache, level 2 cache, andlevel 3 cache. Four priority ranks are set: a line of priority P1 isstored into the caches of all levels 1 to 3 of hierarchy; a line ofpriority P2 is stored into the level 2 and level 3 caches only; a lineof priority P3 is stored into the level 3 cache only; and a line ofpriority P4 is not stored into any level cache. The priority is usedonly when a line is stored into the cache. Suppose that the priority ofa line L1 is P2 and the line 2 is stored in both level 2 and level 3caches at a certain point in time. If the priority of the line L1 isupdated to P3 later, the line L1 should be stored into the level 3 cacheonly. However, the previously stored line L1 remains stored in the level2 cache, which affects the cache hit rate for other lines that areassigned priority P2 and to be stored into the level 2 cache.

[0021] In another mode of embodying the invention, in addition to theabove description, the line and group attribute definitions areseparately assigned on a partition-by-partition basis and the cachememory units in each partition operate, based on the same definitions.Similarly, the policy of storing is separately assigned on apartition-by-partition basis and the cache memory units in eachpartition operate, based on the same policy.

[0022] Each time change is made to the structure of the partitions of acomputer system, the partition manager that is responsible for themanagement of the structure of the partitions assign group definitionsto the group definition tables for all cache memory units included inthe partitions by means of the group definition controller. Similarly,the partition manager assign policy of storing to the policy tables forall cache memory units included in the partitions by means of the policydefinition controller.

[0023] Furthermore, in another mode of embodying the invention, inaddition to the above description, the group definition table containsdata group and instruction group definitions; a line accessed as aresult of that the processor issues an instruction access commandbelongs to the instruction group and a line accessed as a result of thatthe processor issues a data access command belongs to the data group.The group selector determines that the group to which a line belongs isthe instruction group when the line is accessed due to that theprocessor issues an instruction access command. The group selectordetermines that the group to which a line belongs is the data group whenthe line is accessed due to that the processor issues a data accesscommand.

[0024] Features of the present invention other than those describedabove will be disclosed in detailed description of the preferredembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A preferred form of the present invention is illustrated in theaccompanying drawings in which:

[0026]FIG. 1 is a block diagram of a preferred Embodiment 1 of thepresent invention, consisting of one node;

[0027]FIG. 2 is a flowchart illustrating the algorithm of operation ofthe replace line selector in Embodiment 1;

[0028]FIG. 3 shows the group definition table containing example valuesof group definitions that are assigned in a preferred Embodiment 2 ofthe present invention;

[0029]FIG. 4 shows the policy table containing example values that areused with the group definition table in FIG. 3 in Embodiment 2;

[0030]FIG. 5 shows the structure of a command to be used in a preferredEmbodiment 3 of the present invention;

[0031]FIG. 6 shows the group definition table containing example valuesto be used in Embodiment 3;

[0032]FIG. 7 shows the policy table containing example values to be usedin a preferred Embodiment 4 of the present invention;

[0033]FIG. 8 is a block diagram showing a preferred Embodiment 5 of thepresent invention; and

[0034]FIG. 9 shows a partition definition table which is used inEmbodiment 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Embodiment 1

[0036]FIG. 1 shows the configuration of an information processing deviceincluding a cache memory unit embodiment of the present invention. Twoprocessors 1-1 and 1-2 arranged along a processor bus 64 are connectedto a memory controller 2 by an address path 66 and data paths 671 and672. The memory controller 2 is connected to a main memory 4 with datapaths 674 and 673. The processors 1 read instructions from the mainmemory through the memory controller 2 and operate in accordance withthe instructions. The processors 1 send a command 51 to the memorycontroller 2 as required to request the memory controller 2 to read datafrom the main memory or write data into the main memory.

[0037] A cache memory unit 3 of the present invention is installed inthe memory controller 2. According to the command 51 issued from one ofthe processors 1, the memory controller 2 accesses the main storage 4.The memory controller 2 stores the data retrieved by the access to themain memory 3 into the cache memory unit. When one of the processors 1issues a request for the access to that data again, if that data stillremains stored in the cache memory unit 3, the processor 1 uses the datastored in the cache memory unit 3 instead of the data stored in the mainmemory 4.

[0038] The command 51 that the memory controller 2 receives from one ofthe processors 1 includes an operation code (op) 52, an address 53 part,and an instruction/data discrimination bit 56 to discriminate betweeninstruction and data to be accessed. The address 53 part consists of tag54, index 55, and offset fields. The command 51 is 64 bits long and itstenth bit is the instruction/data discrimination bit 56. The memorycontroller 2 has a command register 50 into which the command 51 issuedfrom the processors is stored. When the processors issues the command 51to the memory controller 2, the memory controller 2 stores the commandinto the command register 50.

[0039] Then, the cache memory unit of Embodiment 1 will be explainedbelow.

[0040] [Description of a Cache Memory 35]

[0041] Arranged on a 4-way set-associative scheme, a cache memory 35comprises four cache memory banks: cache memory bank 0 (30), cachememory bank 1 (31), cache memory bank 2 (32), and cache memory bank 3(33). Each cache memory bank comprises, for example, 16 k pieces ofentries, in each of which information for one line is stored. Each entryconsists of control information area and data area. The controlinformation area comprises the fields of tag 300 that is a partial bitstring of the address part, status (S) 301, group identifier (G) 302,and LRU (Least Recently Used) 303 that indicates how long the line dataremains unused since the last time it was accessed. The data areacomprises data area 304. The status 301 field contains one of the fourstatuses: “Modified” indicating that the line data has been modified;“Exclusive” indicating that only one processor is referring to the line;“Shared” indicating that a plurality of processors are referring to theline; and “Invalid” indicating that the line is invalid.

[0042] [Description of a Group Definition Controller 70]

[0043] A group definition controller 70 is a means of registering groupdefinition D (attribute information) that defines a group to which theline belongs and the attribute of the group into a group definitiontable 350; e.g., the group definition controller is the console of theinformation processing device. Alternatively, the group definitioncontroller may be embodied as a memory mapped I/O device with a circuitfor extracting data by decoding the information stored at address. Inshort, the group definition controller may be embodied by using apublicly known technique. The group definition controller may operate asthe definition means to set line and group attribute definitions whichare used for the management of cache memory operation in the groupdefinition table which will be described below.

[0044] [Description of the Group Definition Table 350]

[0045] One line of the group definition table 350 gives the definition Dof a group of a particular attribute. The group definition table 350contains four lines (356, 357, 368, and 359) in which up to four groupscan be defined. Each line to give group definition comprises the fieldsof position Po (351), size Si (352), pattern P1 (353), pattern P2 (354),and group identifier G (355). The position 351 value indicates the leastsignificant bit of the bit string that contains group-identifyinginformation within the bit string of the command 51. The size 352 valueindicates the bit length of the group-identifying information. Thevalues of the patterns P1 and P2 indicate a pattern that is used tocheck for the match between the bit string specified by the position 351and size 352 within the command 51 and this pattern or a pattern rangethat is used to check whether the above bit string falls within thisrange. If the pattern P1 value equals the pattern P2 value, the valueindicates a pattern for matching check. If the pattern P1 value differsfrom the pattern P2 value, these values indicate the pattern range. Thegroup identifier 355 value indicates the identifier of a group to whichthe line to be accessed by that command 51 belongs if the value of thebit string specified by the position 351 and size 352 matches thepattern P1 or falls within the range defined by the pattern P1 and thepattern P2. As for the group definition table 350 illustrated in thepresent embodiment example (FIG. 1), group definitions are registered onits first line 356 and second line 357; i.e., two groups are defined.The position 351 values of group definition on the first line 356 andgroup definition on the second line 357 are 10th bit and the size valueis one bit, which indicates that one bit, the 10th bit of the command51, contains group information. As illustrated in FIG. 1, the 10th bitof the command 51 is the instruction/data discrimination bit 56. Thus,the two groups are distinguished, depending on whether the line isinstruction or data. On the first line 356 of the group definition table350, both the pattern P1 and pattern P2 values are 0 and the groupidentifier 355 is IG (Instruction Group). This means that a group towhich the line to be accessed by the command 51 is an instruction groupif the instruction/data discrimination bit 56 of the command 51 is 0. Onthe second line 357 of the group definition table 350, both the patternP1 and pattern P2 values are 1 and the group identifier 355 is DG (DataGroup). This means that a group to which the line to be accessed by thecommand 51 is a data group if the instruction/data discrimination bit 56of the command 51 is 1.

[0046] [Description of a Group Selector 37]

[0047] A group selector 37 checks a command 51 issued from one of theprocessors 1 against the group definition table 350 and determines whatis the group identifier to which the line to be accessed by the command5 belongs. The group selector 37 determines the group identifier byfollowing the procedure below:

[0048] (1) The group selector first reads one group definition from thegroup definition table 350.

[0049] (2) The group selector reads the bit string specified by theposition 351 and size 351 in the read group definition D from thecommand 51.

[0050] (3) The group selector judges whether the retrieved bit stringmatches the pattern P1 in the group definition D or the value of the bitstring fall's within the range defined by the pattern P1 and pattern P2.

[0051] (4) If the match-up or the range is true in the above step (3),the group selector determines the group identifier 255 in the groupdefinition D as the group to which the line belongs.

[0052] (5) Unless the match-up or the range is true in the above step(3), the group selector refers to another group definition D and repeatsthe above steps (1) to (4).

[0053] In the case of the present embodiment example (FIG. 1), the 10thbit of command 51 contains a value of 0. This matches the value of 0 ofthe pattern 353 in the group definition on the first line 356 of thegroup definition table 350. Therefore, it is determined that the groupto which the line to be accessed by the command 51 is an instructiongroup.

[0054] [Description of a Policy Definition Controller 71]

[0055] A policy definition controller 71 is a means of registeringpolicy of storing that specifies how to store lines into the cachememory in accordance with the line and group attribute into a policytable 360; e.g., the policy definition controller is the console of theinformation processing device. Alternatively, the policy definitioncontroller may be embodied as a memory mapped I/O device with a circuitfor extracting data by decoding the information stored at address. Inshort, the policy definition controller may be embodied by using apublicly known technique.

[0056] [Description of the Policy Table 360]

[0057] A policy table 360 defines policy of storing rules. A set ofgroups is defined on each line of the policy table 360. Each line of thepolicy table 360 comprises the fields of group G1 (361), group G2 (362),group G3 (363), and group G4 (364), each of which to contain one groupidentifier. A set of groups is defined as a set comprising members ofgroups identified by group identifiers contained in the group G1 (361)to G4 (364) fields (some fields may be empty). As up to four groups canbe defined in the group definition table 350, four group fields areprovided in the policy table 360.

[0058] The policy table contains four lines 365, 366, 367, and 368 andfour sets of groups in total are defined in the table. The number ofgroup sets is four because the present cache memory unit 3 is the 4-wayset-associative cache comprising four cache memory banks 30, 31, 32, and33.

[0059] On the first line 365 and second line 366 of the policy table360, a group set {IG} is set that comprises only one member ofinstruction group IG. On the third line 367 and fourth line 368, a groupset {IG DG} is set that comprises instruction group IG and data group DGmembers. The policy table 360 as a whole defines the following policy ofstoring:

({IG}, {IG}, {IG DG}, {IG DG}){circle over (1)}

[0060] This policy of storing means that any two of the four cachememory banks 30, 31, 32, and 33 are used exclusively for lines thatbelong to an instruction group IG and remaining two banks are used forlines that belong to an instruction group or a data group DG. In otherwords, a maximum of four lines belonging to an instruction group IG anda maximum of two lines belonging to a data group DG can be stored intothe same-index entries on the banks (as a set) of the cache memory.Therefore, the same-index entries may be allocated for lines in any ofthe following patterns of combinations of groups to which the linesbelong (which hereinafter are referred to as storing patterns):

(IG, IG, IG, IG) (All lines belong to IG.)  (Pattern 1)

(IG, IG, IG, DG) (Three lines belong to IG and one line belongs toDG.)  (Pattern 2)

(IG, IG, DG, DG) (Two lines belong to ID and two lines belong toDG.)  (Pattern 3)

[0061] The policy of storing in the present embodiment example definesthe number of lines that belong to a group to be retained in thesame-index entries on the banks of the cache and what groups to sharethe corresponding entry locations (of the same index) of the cachememory banks as storing rules. The lines may be stored into any cachememory bank, provided the above number of lines is correct.

[0062] If lines are stored into the cache in accordance with this policyof storing, the lines that belong to an instruction group IG will stayon the cache longer and will be more preferentially handled than thelines that belong to a data group. By specifying desirable policy ofstoring, the user can give higher priority to a certain group of lines.How to store lines into the cache, according to the policy of storing,will be described later with reference to FIG. 2.

[0063] [Description of a Hit Checker 34]

[0064] A hit checker 34 judges whether a line is stored in the cachememory 35 and sets the hit information 60 bit to 1 if the line is stored(this state is called a hit) and the miss information 61 bit to 1 if theline is not stored (this state is called a miss). The hit checker 34corresponds to the hit decision circuit in a typical known cache and maybe embodied by using a publicly known technique.

[0065] [Description of a Replace Line Selector 38]

[0066] A line read from the main memory 4 is to replace any linepreviously stored in the cache memory 35. A replace line selector 38selects a line to be replaced by a new line. The detail on the replaceline selector 38 will be described later in the description ofoperation.

[0067] [Description of a Data Write Unit 39]

[0068] When a line 63 to be replaced by a new line has been selected bythe replace line selector 38, if the status of the line 63 to bereplaced is Modified, a data write unit 39 writes the line back into themain memory 4 and stores the new line into the cache memory bank wherethe line 63 to be replaced has been stored. The data write unit 39corresponds to the data write circuit in a typical known cache and maybe embodied by using a publicly known technique.

[0069] The components of the cache memory unit 3 were explained above.These components of the cache memory unit are put in order as follows.The group definition controller 70, the policy definition controller 71,the hit checker 34, and the data write unit 39 can be embodied by usinga publicly known technique. The cache memory 35 can also embodied byusing a publicly known technique, except the group identifier 392 isadded to the information for each entry. New components are the groupdefinition table 350, the group selector 37, the policy table 360, andthe replace line selector 38.

[0070] Next, the operation of the information processing deviceincluding the cache memory unit 3, shown in FIG. 1, will be explained.

[0071] [Initialization]

[0072] At the startup of this information processing device, groupdefinitions are registered into the group definition table 350 by thegroup definition controller 70 and policy of storing is registered intothe policy table 360 by the policy definition controller 71. Then,software starts to run on the information processing device. Even afterthe start of the software run on the information processing device, thecontents of the group definition table 350 and the policy table 360 maybe modified at any arbitrary time.

[0073] The processors 1 execute processing in accordance with programinstructions and send the command 51 to the memory controller 2 when theaccess to the main memory is required. When the memory controller 2accepts the command 51 stored into its command register 50, it executesprocessing in accordance with the command 51. First, the memorycontroller 2 refers to the cache memory banks 30, 31, 32, 33 in parallelby using the index 55 information in the command 51 as the index andreads the control information (300, 301, 302, 303) parts of the linesstored in the entries indexed by that index on the cache memory banks30, 31, 32, 33. The hit checker 34 compares each of the tags 300 of theread control information parts of the four lines with the tag 54 in thecommand 51. If one of the four tags 300 matches the tag 54, the hitchecker 34 sets the hit information 60 bit to 1, which indicates thatthe line to be accessed by the command 51 has been hit on the cache. Ifnone of the tags 300 match the tag 54, the hit checker 34 sets the missinformation 61 bit to 1, which indicates that the line to be accessed bythe command 51 is missing on the cache.

[0074] When the hit checker 34 sets the hit information 60 bit to 1, thecache memory unit 3 accesses the entry indexed by the index 55 in thecache memory bank where the tag 300 that matched the tag 54 exists. Ifthe command 51 is read, the cache memory unit 3 reads the line from thedata area 304 of that entry and returns it to the processor 1 thatissued the command. If the command 51 is write, the cache memory unit 3writes the data and control information sent from the processor thatissued the command into the data area 304 of that entry. When the hitchecker 34 sets the miss information 61 bit to 1, the cache memory unit3 accesses the main memory 4, reads a line from the address 53 specifiedin the command 51, and returns the line to the processor 1 that issuedthe command. At the same time, the cache memory unit 3 stores the line(which is hereinafter referred to as the line to be stored) into thecache memory. To store the line to be stored into the cache memory,first, the replace line selector 38 selects a line to be replaced out offour lines (which are hereinafter referred to as candidate lines to bereplaced) stored in the entries indexed by the index 55 on the cachememory banks 30, 31, 32, and 33. The detail on how to select a line tobe replaced will be described later. When the replace line selector 38has selected a line 63 to be replaced, if the status of the line 63 tobe replaced is Modified, the data write unit 39 writes the line backinto the main memory and stores the line to be stored into the entrylocation indexed by the index 55 in the cache memory bank where the lineto be replaced has been stored. At this time, the group identifier 62(determined by the group selector) to which the line to be storedbelongs is stored into the group identifier 302 field.

[0075] Modification to the contents of the group definition table 70 bythe group definition controller 70 or modification to the contents ofthe policy table 360 by the policy definition controller 71 during theoperation of the information processing device affects only theprocessing to be executed by the replace line selector 38, but theprocessing of the cache control unit 3 components other than the replaceline selector 38 is all the same as described above.

[0076] Then, the detail on the operation of the replace line selector 38will be described below.

[0077] The replace line selector 38 selects a line to be replaced out offour candidate lines to be replaced by using the control information(status 301, group identifier 302, and LRU 303) for the four candidatelines, the group identifier 62 of the group to which the line to bestored belongs, determined by the group selector 37, and the policytable 360. The operation of the replace line selector is explained withreference to FIG. 2. Symbols used for explanation are defined below:

[0078] Li: Line stored in cache memory bank i among the candidate linesto be replaced

[0079] Lr: Line to be stored

[0080] GI: Group identifier (IG or DG in the present embodiment example)

[0081] S (Li): Status of line Li

[0082] G (Lk): Group to which line Lk belongs

[0083] L (Gj): The number of lines belonging to group Gj among thecandidate lines L1 , . . . , L4 to be replaced

[0084] P (Gj): The number of group sets comprising or including a groupGj member among the group sets of the policy of storing.

[0085] Among the group sets of the policy of storing defined in thepolicy table 360 (FIG. 1), the number of group sets comprising orincluding an instruction group IG member is four; P (IG)=4 and thenumber of group sets including a data group DG member is two; P (DG)=2.

[0086] The replace line selector 38 operates as follows.

[0087] [Operation of the Replace Line Selector]

[0088] (1) In step 1001, the replace line selector first checks to seewhether there is a line Li with its status S (Li) being “Invalid”(S(Li)=Invalid) among the candidate lines L1, . . . , L4 to be replaced.If there is a line Li with S (Li)=Invalid, the selector determines thatline as the line to be replaced in step 1002. If there are a pluralityof lines Li with S (Li)=Invalid, the selector arbitrarily selects one ofthese lines Li (for example, according to LRU) and determines that lineas the line to be replaced. The operation in the step 1002 under thecondition of the step 1001 is the same as usual cache operation underthe same condition (as in the step 1001).

[0089] If, for example, all candidate lines to be replaced are put in“Invalid” status and four same-index lines belonging to a data group DGare to be stored in series into the cache memory, all entry locationscorresponding to that index in the cache memory are filled with thelines belonging to the group DG. This does not match any of theabove-mentioned storing patterns (pattern 1, pattern 2, and pattern 3)of the policy {circle over (1)} of storing defined in the policy table360 and does not comply with the policy {circle over (1)} of storing,but this is acceptable. The reason for that is as follows. If the linesare stored exactly in compliance with the policy of storing defined inthe policy table 360 in FIG. 1, only two lines belonging to a data groupDG are stored into the cache, whereas the corresponding entries on theremaining two cache memory banks remain empty. This manner is worse inefficiency than the above manner disregarding the policy. In the presentembodiment example, thus, if there is a line put in “Invalid” status,such a method, which is, however, nonconformity to the policy ofstoring, is taken that the line should be replaced by the line to bestored into the cache, whatever group the line belongs to. Even if thismethod is taken, the policy of storing will be followed if two or morelines belonging to an instruction group IG are later to be stored intothe entry locations indexed by the same index as for the previouslystored lines.

[0090] Exception to the policy may occur as noted above; i.e., a storingpattern in which the lines actually stored into the cache memory belongsto a group or groups does not match any of the storing patterns of thegroup sets defined in the policy of storing (this is referred to as adeviant case from the policy.) In addition to the above exception, thereis another exception. This exception occurs when the policy of storingis changed, though grouped lines were originally stored into the cachememory in conformity with one of the patterns of the policy of storing.For such exception, the replace line selector operates for storing thelines as will be described under items (2) and (3) below so that thepattern in which grouped lines are stored into the cache will match anyof the patterns defined in the policy of storing.

[0091] (2) If the condition specified for the step 1001 is notsatisfied, the procedure goes to step 1003. Here, if relation of L (G(Lr))≧P (G (Lr)) is true, where L (G (Lr)) is the number of candidatelines L1, . . . , L4 to be replaced that meets the condition that theline belongs to the group G (Lr) to which the line Lr to be storedbelongs and P (G (Lr)) is the number of group sets defined in the policyof storing that meets the condition that the group set comprises orincludes the member of the group G (Lr) to which the line Lr to bestored belongs, the replace line selector executes step 1004. In thestep 1004, among the candidate lines L1 , . . . , L4 to be replaced, theselector targets the lines Li belonging to group G (Li) that is the sameas the group G (Lr) to which the line Lr to be stored belongs (G (Li)=G(Lr)), and determines the line to be replaced by selecting out of thelines Li, based on the LRU information for each line Li.

[0092] Condition of L (G (Lr))=P (G (Lr)) included in the condition of L(G (Lr))≧P (G (Lr) indicates that the number of candidate lines to bereplaced that belong to the group G (Lr) is the maximum number of linesbelonging to the group G (Lr) that can be stored into the cache memoryin the entry locations indexed by the same index specified in the policyof storing. If L (G (Lr))=P (G (Lr)) is true, the replace line selectordetermines the line to be replaced by selecting out of the candidatelines to be replaced that belong to the group G (Lr). Condition of L (G(Lr))>P (G (Lr) ) is satisfied in the deviant case from the policy,which was described under the above item (1). Even in this case,similarly, the replace line selector determines the line to be replacedby selecting out of the candidate lines to be replaced that belong tothe group G (Lr).

[0093] In the present embodiment example, the policy of storing{circumflex over (1)} defined in the policy table 360 gives, forexample, P (IG)=4 and P (DG)=2. If the line Lr to be stored is a linebelonging to an instruction group IG, and if the condition of L (IG)>4is satisfied where L (IG) is the number of candidate lines to bereplaced that belong to an instruction group IG, the replace lineselector determines the line to be replaced by selecting out of thecandidate lines to be replaced that belong to an instruction group.(Because the maximum number of L (IG) is four corresponding to thenumber of ways of the cache memory 35, it is impossible for aninstruction group IG that L (IG) becomes less than 4 (i.e., the deviantcase from the policy is impossible to occur.)) If the line Lr to bestored is a line belonging to a data group DG, and if the condition of L(DG)≧2 is satisfied where L (DG) is the number of candidate lines to bereplaced that belong to a data group DG, the replace line selectordetermines the line to be replaced by selecting out of the candidatelines to be replaced that belong to a data group DG.

[0094] (3) If both conditions specified for the steps 1101 and 1003 arenot satisfied, the procedure goes to step 1005. Here, if relation L(Gj)>P (Gj) is true, where L (Gj) is the number of lines Li that belongto group Gj different from the group G (Lr) to which the line Lr to bestored belongs (G (Li)=Gj) and P (Gj) is the number of group setsdefined in the policy of storing that meets the condition that the groupset comprises or includes the group Gj member, the replace line selectorexecutes step 1006. In the step 1006, among the candidate lines L1, . .. , L4 to be replaced, the selector targets the lines Li belonging togroup G (Li) that is the group Gj (G (Li)=Gj) and determines the line tobe replaced by selecting out of the lines Li, based on the LRUinformation.

[0095] Condition of L (Gj))>P (Gj) is satisfied in the deviant case fromthe policy, which was described under the above item (1). Ifcircumstances take place where the application of the policy of storingis not suitable (the deviant case from the policy), the replace lineselector targets the lines belonging to group Gr other than the group G(Lr) to which the line to be stored belongs and determines the line tobe replaced by selecting out of the lines belonging to the group Gr. Bythis operation, the pattern in which grouped lines are stored into thecache memory approximates to any of the patterns of the policy ofstoring.

[0096] In the present embodiment example, if the line Lr to be storedis, for example, a line belonging to an instruction group IG, and if thenumber of candidates lines to be replaced belonging to a data group DG,namely L (DG) satisfies the condition of L (DG)>2, the replace lineselector determined the line to be replaced by selecting out of thecandidate lines belonging to a data group. If the line to be stored is aline belonging to a data group DG, because the number of candidate linesto be replaced belonging to an instruction group IG, namely L (IG) is≦4,the condition specified for the step 1005 is not satisfied.

[0097] (4) All the conditions specified for the steps 1001, 1003, and1005, the procedure goes to step 1007. Here, the replace line selectortargets the lines belonging to group Gk that is a member joined a groupset that also includes the group G (Lr) member to which the line Lr tobe stored belongs. The replace line selector determines the line to bereplaced by selecting out of the lines belonging to the group Gk,according to the LRU information.

[0098] In the case of the present embodiment, if the line LR to bereplaced belongs to, for example, an instruction group IG, the replaceline selector targets the lines belonging to a data group DG that is amember joined a group set that also includes an instruction group IGamong the group sets of the policy {circle over (1)} of storing (thepolicy {circle over (1)} of storing includes a group set {IG DG} thatincludes the member of an instruction group IG). Then, the selectordetermines the line to be replaced by selecting out of the targetedlines. If the line LR to be replaced belongs to a data group DG, thereplace line selector targets the lines belonging to an instructiongroup ID that is a member joined a group set that also includes a datagroup DG among the group sets of the policy {circle over (1)} of storing(the policy {circle over (1)} of storing includes a group set {IG DG}that includes the member of a data group DG) Then, the selectordetermines the line to be replaced by selecting out of the targetedlines.

[0099] Next, the effect of the cache memory unit 3 of Embodiment 1 willbe explained. First, consider a case (normal case) where grouped linesare stored into the entry locations indexed by an index on the banks ofthe cache memory 35 in conformity with any of the storing patterns(pattern 1), (pattern 2), and (pattern 3) of policy {circle over (1)} ofstoring defined in the policy table 360. By way of example, consider acase where line A and line B that belong to an instruction group IG andline C and line D that belong to a data group DG are stored in theentries indexed i on the banks of the cache memory 36. Because thegrouped lines are stored in the entries indexed i on the banks in thepattern (IG, IG, DG, DG), this pattern conforms to the storing pattern(pattern 3) of the policy {circle over (1)} of storing. When the cacheis in the state described above, suppose that new lines E, F., G, and Hthat are assigned index i and belong to a data group are to be stored inseries into the cache memory 35. Because all these lines are new and donot exist in the cache memory 35, each of them shall replace any of thepreviously stored lines in the entries indexed i on the banks of thecache memory.

[0100] Storing the line E is first explained below. The line to bereplaced by the line E when storing the line E is determined inaccordance with any of the foregoing operation procedure items 1 to 4 ofthe replace line selector 38. Because none of the lines stored in theentries indexed i on the banks are put in “Invalid” status and therelation of L (DG)=P (DG) is true for a data group DG to which the lineE belongs, the replace line selector executes item (2) of the procedureitems (1) to (4) described under [Operation of the replace lineselector]. Among the lines stored in the entries indexed i on the banksof the cache memory, the selector targets the lines C and D belonging toa data group and determines the line to be replaced by selecting themost suitable one (for example, the line C), according to LRU. Then, theline E is stored into the entry where the thus determined line exists,replacing this old line. After this storing action, the lines stored inthe entries indexed i on the banks of the cache memory 35 become A, B,D, and E and this pattern in which the grouped lines are stored conformsto the storing pattern (pattern 3) of the policy {circle over (1)} ofstoring. After other new lines F, G, and H are similarly stored into thecache, the lines stored in the entries indexed i on the banks of thecache memory 35 eventually become A, B, G, and H.

[0101] In the present embodiment example, the processing for storing thenew lines is performed in conformity with the policy of storing in thisway and the lines A and B belonging to an instruction group IG are notreplaced by the lines belonging to the group DG. Even after the lines E,F, G, and H are written into the cache memory, the lines A and B remainon the cache memory. When the cache is accessed for reference to theline A or B after the line H is stored, the line search will be a hit.

[0102] Meanwhile, for comparison purposes, for the same example case asdescribed, suppose that the example lines are stored into a typicalknown cache which is based on the method of storing all lines equally.In this case, the line to be replaced is determined withoutdiscrimination between the lines belonging to an instruction group IGand the lines belonging to a data group DG. Thus, the lines A and B arereplaced by any of the lines E, F, G, and H and eventually, the linesstored in the entries indexed i on the banks of the cache memory 35become E, F, G, and H. In this case, when the cache is accessed forreference to the line A or B after the line H is stored, the line searchwill be a miss.

[0103] As evident from the above example case, if the probability ofreusing the lines belonging to an instruction group is higher and theprobability of reusing the lines belonging to a data group lower, and ifthe latter lines are more frequently accessed than the former lines, ina typical known cache, a line belonging to an instruction group isreplaced by a line belonging to a data group, though the former line ismore likely to be reused than the latter line, resulting in a low hitrate of the cache memory. In contrast, in the present embodiment of theinvention, a line belonging to an instruction group is morepreferentially stored into the cache than a line belonging to a datagroup as in the policy {circle over (1)}. Thus, a line that belongs toan instruction group and is more likely to be reused is less replaced bya line that belongs to a data group and is less likely to be reused.Consequently, the present invention produces effect: the cache hit rateincreases; and the invention can achieve higher performance of theinformation processing device using the cache configured by theinvention than the corresponding device equipped with a typical knowncache.

[0104] The cache configured by the invention is adaptive to dynamicchange to the policy of storing, which will be explained below. Beforechange to the policy occurs, suppose that the lines A and B belonging toan instruction group IG and the lines C and D belonging to a data groupDG are stored in the entries indexed i on the banks of the cache memory35, according to the policy {circle over (1)} of storing defined in thepolicy table 360 in FIG. 1. The grouped lines are stored in the entriesindexed i on the banks of the cache memory 35 in the pattern (IG, IG,DG, DG) which conforms to the storing pattern (pattern 3) of the policy{circle over (1)} of storing. When the cache is in this state, assumethat policy {circle over (1)} of storing as new policy has now beenregistered in to the policy table by the policy definition controller71. The policy {circle over (2)} of storing is as follows:

({IG}, {IG}, {IG}, {IG DG}) {circle over (2)}

[0105] The change to the policy {circle over (1)} to the policy {circleover (2)} of storing means that priority of storing is given to a linebelonging to a data group. The pattern in which the lines A, B, C, and Dare stored does not conform to the policy {circle over (2)} of storing.Under this state, assume that a new line E belonging to an instructiongroup E is to be stored. None of the lines indexed by i are in “Invalid”status in the cache memory 35. Because of L (IG)=2 for an instructiongroup IG, the relation of L (IG)≧P (IG) is true. At the same time,because of L (DG)=2 for an instruction group IG, the relation of L(DG)≧P (DG) is true. Thus, the replace line selector 38 executes item(3) of the procedure items (1) to

[0106] (4) described under [Operation of the replace line selector]. Theselector targets the lines C and D belonging to a data group anddetermines the line to be replaced by selecting the most suitable one(for example, the line C), according to LRU. Then, the lines A, B, D,and E are stored in the entries indexed i on the banks of the cachememory. These lines are stored in the pattern (IG, IG, IG, DG) whichconforms to the pattern of the policy 2. Thus, the cache is adaptable todynamic change to the policy of storing, which is one of the advantagesof the present cache embodiment of the invention.

[0107] The cache memory unit 3 of Embodiment 1 is installed in thememory controller 2 and refers to the tag 54, index 55, andinstruction/data discrimination bit 56 information in a command issuedfrom a processor. Because all of such information is included in acommand that is normally issued from typical known processors, the cachememory unit 3 can be embodied only by changing the memory controllerwithout changing the processors 1. Thus, this solves problem 3, which isone of the advantages of the present cache embodiment of the invention.

[0108] Embodiment 2

[0109] A cache as a preferred Embodiment 2 of the invention isconfigured the same as shown in FIG. 1 of Embodiment 1. Only the changeis the values to be assigned to the tables. The values given in thegroup definition table 350 in FIG. 1 changed to those in a groupdefinition table 3501 which is shown in FIG. 3. The values given in thepolicy table 360 in FIG. 1 changed to those in a policy table 3601 whichis shown in FIG. 4. With the exception of these two tables and the groupselector 37 and the replace line selector 38, shown in FIG. 1, thatoperate, depending on the values of the tables, other components areconfigured and operate as in Embodiment 1.

[0110] In the group definition table 3501 in FIG. 3, definitions of twogroups are registered on its first line 356 and second line 357. Thetable may contain definitions of three or more groups. The groupdefinition on the first line 356 means that the identifier of a group towhich a line to be accessed by a command belongs is G1 if the string ofthe 24th to 39th bits of the command 51, shown in FIG. 1, falls withinthe range from 0×0000 to 0×1200. The group definition on the second line357 means that that the identifier of a group to which a line to beaccessed by a command belongs is G2 if the string of the 24th to 39thbits of the command 51, shown in FIG. 1, falls within the range from0×0×1201 to 0×BE00. Because the 24th to 39th bits of the command 51 arepart of the address 53 part, lines are grouped by the address of theline to be accessed.

[0111] According to the group definition table 3501 in FIG. 3, the groupselector 37 shown in FIG. 1 distinguishes a group to which the line tobe accessed by the command 51 belong as follows. When the string of the24th to 39th bits of the command 51 falls within the range from 0×0000to 0×1200, the group selector finds G1 as the identifier of the group towhich the line to be accessed by the command belongs. When the string ofthe 24th to 39th bits of the command 51 falls within the range from0×0×1201 to 0×BE00, the group selector finds G2 as the identifier of thegroup to which the line to be accessed by the command belongs.

[0112] In the policy table 3601 in FIG. 4, the group identifiers G1 andG2 defined in the group definition table 3501 are used; the former G1replacing the instruction group IG in the policy table 360 in FIG. 1 andthe latter G2 replacing the data group DG in the policy table 360 inFIG. 1. With the exception of the group identifiers, the policy table3601 in FIG. 4 serves all the same as the policy table 360 in FIG. 1does. Because the policy table 3601 in FIG. 4 is all the same as thepolicy table 360 in FIG. 1 except for the group identifiers, the replaceline selector 38, shown in FIG. 1, that selects a line to be replacedwhile referring to the policy table 3601 also operates in all the sameway as described under [Operation of the replace line selector] inEmbodiment 1, except that different group identifiers are used.

[0113] As implied above, Embodiment 2 substantially differs fromEmbodiment 1 in the group definitions and the method of distinguishinggroups. Thus, Embodiment 2 produces much the same effect as Embodiment1, but there is some difference of effect by the different manner ofgroup definition. In Embodiment 1, the lines belonging to an instructiongroup is stored into the cache memory 35 more preferentially than thelines belonging to a data group, but the lines in an instruction groupor a data group are treated equally. As for the lines in one group, thesame problem is posed as for a typical known cache that equally treatsthe lines. In contrast, in Embodiment 2, the lines are grouped by theline address; thereby, for example, even the lines belonging to a datagroup can be classified into subgroups. Embodiment 2 enables that a lineclassified as a subgroup is more preferentially stored into the cachememory 35 than a line classified as another subgroup, which can increasethe cache hit rate, according to circumstances. This is advantage ofEmbodiment 2. In some case, the application of Embodiment 1 can achievehigher performance of the cache; in other case, the application ofEmbodiment 2 can achieve higher performance of the cache. This mainlydepends on the nature of the program to be executed. Furthermore,grouping the lines into instruction and data groups as in Embodiment 1and grouping the lines by the line address as in Embodiment 2 may bemixed and specified in the group definition table 350. In this manner,more flexible cache operation can be expected than as in Embodiment 1 orEmbodiment 2 and the cache is likely to achieve higher performance.

[0114] Embodiment 3

[0115] A cache as a preferred Embodiment 3 of the invention isconfigured the same as shown in FIG. 1 of Embodiment 1. Only the changeto Embodiment 1 is as follows. A command 511 which is shown in FIG. 5 isused instead of the command 51 shown in FIG. 1. The values given in thegroup definition table 350 in FIG. 1 changed to those in a groupdefinition table 3502 which is shown in FIG. 6. The values given in thepolicy table 360 in FIG. 1 changed to those in the policy table 3601which is shown in FIG. 4. The policy table 3601 in FIG. 4 is used asexplained in Embodiment 2. Because the given policy table and the groupidentifiers G1 and G2 for distinguishing the groups are the same as inEmbodiment 2, the replace line selector 38 operates in the same way asin Embodiment 2. With the exception of the command 511, the groupdefinition table 3502, and the group selector 37 that operates,depending on this table, other components of the cache memory unit 3 arethe same as in Embodiment 1 or Embodiment 2.

[0116] The command 511 shown in FIG. 5 is modification to the command 57to which the group identifier 57 is added in the 4th and 5th bits. It isobvious that a group to which a line to be accessed by the command 511belongs is the group identified by the group identifier 57 in thecommand. The group identifier is intended to allow the user to specify agroup to which data belongs in a program or a compiler to specify agroup to which data belongs.

[0117] In the group definition table 3502 shown in FIG. 6, definitionsof two groups are registered on its first line 356 and second line 357.The table may contain definitions of three or more groups. The groupdefinition on the first line 356 means that the identifier of a group towhich a line to be accessed by a command belongs is G1 if the two 4thand 5th bits of the command 511, shown in FIG. 5, contain “01.” Thegroup definition on the second line 357 means that the identifier of agroup to which a line to be accessed by a command belongs is G2 if thetwo 4th and 5th bits of the command 511, shown in FIG. 5, contain “10.”

[0118] According to the group definition table 35021 in FIG. 6, thegroup selector 37 shown in FIG. 1 distinguishes a group to which theline to be accessed by the command 511 belong as follows. If the two 4thand 5th bits of the command 511 contain “01,” the group selector findsG1 as the identifier of the group to which the line to be accessed bythe command belongs. If the two 4th and 5th bits of the command 511contain “10,” the group selector finds G2 as the identifier of the groupto which the line to be accessed by the command belongs.

[0119] As implied above, Embodiment 3 substantially differs fromEmbodiment 1 and Embodiment 2 only in group definitions and the methodof distinguishing groups. Thus, Embodiment 3 produces much the sameeffect as Embodiment 1, but there is some difference of effect by thedifferent manner of group definition. In Embodiment 1, lines are groupedinto two groups: instruction group and data group. This grouping israther rough and may be ineffective in some case. In Embodiment 2,because lines are grouped by the line address, fine grouping can be setif the address range of one group is set small and many groups aredefined. However, this method is accompanied by a problem that the sizeof the group definition table becomes larger and it takes longer time todistinguish a group. On the other hand, the method of Embodiment 3allows the user or compiler to specify a line to be storedpreferentially into the cache or a line not to be so for any part of aprogram and fineness of grouping can be set almost arbitrarily. Due tothis, higher performance of the cache can be achieved in Embodiment 3 insome case, though the cache performance is not enhanced significantly inEmbodiments 1 and 2. This is advantage of Embodiment 3.

[0120] Embodiment 4

[0121] A cache as a preferred Embodiment 4 of the invention isconfigured the same as shown in FIG. 1 of Embodiment 1. Only the changeto Embodiment 1 is as follows. The values given in the policy table 360in FIG. 1 changed to those in a policy table 3603 which is shown in FIG.7. With the exception of the policy table 3603 and the replace lineselector 38 that operates, depending on this table, other components ofthe cache memory unit 3 are all the same as in Embodiment 1.

[0122] The policy table 3603 shown in FIG. 7 defines the followingpolicy of storing, comprising group sets, each of which comprises onegroup member:

({IG}, {IG}, {IG}, {DG} {circle over (3)}

[0123] This means that, among the lines to be stored into the entriesindexed i on the banks of the cache memory 35 in FIG. 1, three linesbelong to an instruction group IG and the remaining one line belongs toa data group DG. That is, this policy {circle over (3)} of storing meansthat the cache memory 35 is logically divided into the area allocatedfor lines belonging to an instruction group and the area allocated forlines belonging to a data group. Although this policy {circle over (3)}of storing only specifies the number of lines belonging to aninstruction group and the number of a line belonging to a data groupamong the lines that can be stored into the same-index entries, themapping between the lines and the cache memory banks to store them ofthe cache memory 35 may be specified. In the latter case, counting thenumber of lines belonging to a group to be stored into the same-indexentries on the banks of the cache memory can be omitted and processingis simplified.

[0124] The replace line selector 38, shown in FIG. 1, operates forprocessing in Embodiment 4 in the same way as explained in Embodiment 1.

[0125] Because the replace line selector 38 basically operates,according to the same algorithm as for Embodiment 1, its effect is muchthe same as produced in Embodiment 1, but there is some difference. Aslines are stored in conformity with the policy {circle over (1)} ofstoring in Embodiment 1, there is a possibility of replacing a linebelonging to an instruction group by a line belonging to a data group.For example, if four lines A, B, C, and D are stored in the entriesindexed i on the banks of the cache memory 35 all belong to aninstruction group IG and a new line E belonging to a data group DG islater stored into one of these entries of the cache, any one of thelines A to D is replaced by the line E. Therefore, how lines belongingto an instruction group are stored into the cache as well as how linesbelonging to a data group are stored into the cache affect the cache hitrates of the former lines and the latter lines. Specifically, if linesbelonging to a data group are frequently stored into the cache and theprobability of reusing them is relatively low, the cache hit rate oflines belonging to an instruction group also decreases. This problem isthe same one that inevitably arises in a typical known cache into whichall lines are equally stored. On the other hand, in Embodiment 4, withthe exception of the deviant case from the policy, which was explainedin Embodiment 1, a line belonging to an instruction group IG is notreplaced by a line belonging to a data group DG and vise versa.Therefore, in Embodiment 4, the cache hit rate of lines belonging to aninstruction group IG entirely depends on how these lines are stored intothe cache. Similarly, the cache hit rate of lines belonging to a datagroup DG entirely depends on how these lines are stored into the cache.The lines of one group and the lines of another group do not mutuallyaffect the cache hit rate of the other group lines. Consequently, theabove-mentioned problem of Embodiment 1 does not arise and a stablecache hit rate can be expected. This is advantage of Embodiment 4.

[0126] Embodiment 5

[0127] A preferred Embodiment 5 of the invention is an example ofmodification to Embodiment 1. FIG. 8 shows the configuration ofEmbodiment 5. Eight processors 1-1 to 1-8 shown in FIG. 8 are the sameas the processor 1-1 shown in FIG. 1. Four memory controllers 2-1 to 2-5shown in FIG. 8 are the same as the memory controller 2 shown in FIG. 1.A main memory 4 shown in FIG. 8 has the same capability as the mainmemory 4 shown in FIG. 1, but with a plurality of ports, which is adifferent point from the main memory in FIG. 1. Processor buses 64-1 to64-4 shown in FIG. 8 are the same as the processor bus 64 shown inFIG. 1. Address paths 66-1 to 66-4 shown in FIG. 8 are the same as theaddress path 66 shown in FIG. 1. Data paths 671-1 to 671-4 shown in FIG.8 are the same as the data path 671 shown in FIG. 1. Data paths 672-1 to672-4 shown in FIG. 8 are the same as the data path 672 shown in FIG. 1.A group definition controller 700 shown in FIG. 8 functions much thesame as the group definition controller 70 shown in FIG. 1. However, thegroup definition controller 700 is used to register group definitioninto the group definition table 350, shown in FIG. 1, in the specifiedmemory controller among the memory controllers 2-1 to 2-4 in FIG. 8,which is a different point from the group definition controller 70 inFIG. 1. A policy definition controller 710 shown in FIG. 8 functionsmuch the same as the policy definition controller 71 shown in FIG. 1.However, the policy definition controller 710 is used to register policyinto the policy table 360, shown in FIG. 1, in the specified memorycontroller among the memory controllers 2-1 to 2-4 in FIG. 8, which is adifferent point from the policy definition controller 71 in FIG. 1. Apath 680 shown in FIG. 8 makes the connection between the groupdefinition controller 700 in FIG. 8 and the memory controllers 2-1 to2-4 in FIG. 8. A path 690 shown in FIG. 8 makes the connection betweenthe policy definition controller 710 in FIG. 8 and the memorycontrollers 2-1 to 2-4 in FIG. 8.

[0128] Two processors connected by a processor bus and a memorycontroller that is connected to the processor bus will be referred to asa node hereinafter. Nodes, having memory controllers 2-1, 2-2, 2-3, and2-4, respectively, are referred as node 1, node, 2, node 3, and node 4.Embodiment 5 is configured such that the four nodes share one mainmemory. This information processing device can be divided into aplurality of partitions, each of which comprises one ore mode nodes andcan operate as an independent information processing unit. A partitiondefinition table 800 which is shown in FIG. 9 defines the relationbetween the nodes and the partitions; what node belongs to whatpartition. This table contains a set of values assigned by the user byusing a means that can be embodied by a publicly known technique, forexample, such as a console. One partition is defined on each of thelines 805 to 808 of the partition definition table 800. A maximum offour partitions can be defined. Columns 801 to 804 of the tablecorrespond to nodes 1 to 4. If a value of 1 is set in the column of anode on a partition line, it indicates that the node belongs to thepartition. As for the partition definition table illustrated in FIG. 9,the set values indicate that partition P1 comprises nodes 1 and 2,partition P2 comprises node 3, and partition P3 comprises node 4.Although the information processing device is divided into threepartitions in the present example of Embodiment 5, the device, ofcourse, may be used as a whole unit without being partitioned.

[0129] Then, the operation of Embodiment 5 will be explained below. Theoperation of Embodiment 5 is much the same as the operation ofEmbodiment 1, but differs in the procedure of “initialization” of thetables and modifying the group definitions and the policy of storing inthe tables.

[0130] Initialization for Embodiment 5 is performed as follows.

[0131] Group definitions to be set for a partition P1 are registeredthrough the group definition controller 700 in FIG. 8 into the groupdefinition tables 350 in the memory controllers of all nodes that belongto the partition P1. By referring to the partition definition table 800shown in FIG. 9, it is understood that nodes 1 and 2 belong to thepartition P1. Thus, the group definitions are registered into the groupdefinition tables in the memory controllers 2-1 and 2-2 of the nodes 1and 2. Then, group definitions to be set for a partition 2 areregistered into the group definition tables 350 in the memorycontrollers of all nodes that belong to the partition P2. Finally, groupdefinitions to be set for a partition P3 are registered into the groupdefinition tables 350 in the memory controllers of all nodes that belongto the partition P3.

[0132] Similarly, policy of storing to be set for the partition P1 areregistered through the policy definition controller 710 in FIG. 8 intothe policy tables 360 in the memory controllers of all nodes that belongto the partition P1. Policy of storing to be set for the partition P2are registered into the policy tables 360 in the memory controllers ofall nodes that belong to the partition P2. Grouping patterns (policy ofstoring) to be set for the partition P3 are registered into the policytables 360 in the memory controllers of all nodes that belong to thepartition P3. After the above initialization is completed, the nodesoperate all the same as in Embodiment 1.

[0133] When the group definitions and the policy of storing for apartition are modified, through the group definition controller 700 andthe policy definition controller 710, register new group definitions andpolicy of storing into the group definition tables 350 and the policytables 360 in the memory controllers of the nodes that belong to thepartition in the same way as for the above initialization. Then, thenodes within the partition operate all the same as in Embodiment 1.

[0134] The effect of Embodiment 5 is that different group definitionsand policy of storing can be specified for each partition as obviousfrom the above description of initialization operation.

[0135] As regards installing the cache on an LSI in the configurationsof the above Embodiments, the cache memory unit may be installed withinthe processor LSI; alternatively, it may be installed within the memorycontroller LSI that is placed between the processors and the main memoryand controls the access of the processors to the main memory. In thelatter case, however, the embodiments are feasible only by modifying theinformation processing system and can provide the cache memory unit of,higher performance than a typical known cache that treats the linesequally.

[0136] The foregoing invention has been described in terms of preferredembodiments. However, those skilled, in the art will recognize that manyvariations of such embodiments exist. Such variations are intended to bewithin the scope of the present invention and the appended claims.

What is claimed is:
 1. A cache memory unit comprising: a cache memory,placed between processors and a main memory, to temporarily store datain units of lines of given size retrieved from the main memory and storecontrol information associated with data of the lines it retains; agroup definition controller that is used to define grouping of lines tobe put under management; a group selector to determine one of aplurality of groups defined by means of said group definition controlleras the group to which a line to be fetched belongs, according to theinformation in a command that has been issued from one of the processorsto fetch data from said main memory; a policy definition controller thatis used to set policy of storing whereby to store lines into thesame-index entries on the banks of the cache memory in one of thepatterns of combinations of a plurality of groups, to any of which thelines belong, according to said grouping; a hit checker to judge whethera line specified to be read in the command from one of the processorsremains stored on the cache memory; a replace line selector to determinea line to be replaced and removed from the cache memory in accordancewith the group to which a new line belongs, determined by said groupselector, the line control information retained in said cache memory forthe candidate lines to be replaced, and the policy of storing set bymeans of said policy definition controller if the judgment of said hitchecker is a missed hit; and a storing means to retrieve said linespecified to be read from the main memory and store the line withcontrol information for the line in place of the line determined to bereplaced by said replace line selector into the cache memory if thejudgment of said hit checker is a missed hit.
 2. The cache memory unitaccording to claim 1, wherein: said control information associated witheach line that said cache memory retains includes the status of theline, the attribute of the line, and the LRU information that indicatesthe last time the line was accessed.
 3. The cache memory unit accordingto claim 1, wherein group definitions to be set by means of said groupdefinition controller are such that a line accessed as a result of thatone of the processors issues an instruction access command to access aninstruction is the line belonging to an instruction group as itsattribute and a line accessed as a result of that one of the processorsissues a data access command to access data is the line belonging to adata group as its attribute; and said group selector determines thegroup to which a line belongs, depending on whether the line is accessedas a result of that said processor issues an instruction access commandor a data access command, based on the group definitions.
 4. The cachememory unit according to claim 1, wherein: group definitions to be setby means of said group definition controller are such that address spaceof the main memory is divided into m (≧1) pieces of non-overlappingaddress space sections and a address space section allocated for a lineis defined as the attribute of the line; and said group selectordetermines the attribute of a line, according to the address spacesection within which the address of the object line falls, specified inthe command issued from one of the processors.
 5. The cache memory unitaccording to claim 1, wherein: group identifiers representing m (≧1)pieces of group attributes are predetermined: one of the groupidentifiers is embedded into a command issued from one of theprocessors; group definitions to be set by means of said groupdefinition controller are such that the attribute of a group to whichdata accessed by the command belongs is identified by the groupidentifier embedded in the command; and said group selectordistinguishes the group attribute of a line accessed by a command issuedfrom one of the processors by referring to one of the group identifiersembedded in the command.
 6. The cache memory unit according to claim 1,wherein: group identifiers representing m (≧1) pieces of groupattributes are predetermined: and said policy definition controller isused to assign sets Pk={Gi, . . . , G1} (hereinafter referred to asgroup sets) as many (P1, . . . , Pn) as the number of memory banks n ofthe cache memory, each group set consisting of one or more members outof group identifiers G1, . . . , Gm, as the policy of storing.
 7. Thecache memory unit according to claim 6, wherein group sets P of thepolicy of storing, which are assigned by means of said policy definitioncontroller, are the sets (P={G}), to each of which a single group memberis assigned.
 8. The cache memory unit according to claim 7, wherein saidpolicy definition controller is used to assign group sets as many as thenumber of memory banks n of the cache memory and moreover the one-to-onemapping between the group sets and the memory banks of the cache memoryas the policy of storing.
 9. The cache memory unit according to claim 2,wherein: said replace line selector refers to the object subpart of theaddress part of a command issued from one of the processors, determinesa set of the same-index entries on the banks of the cache memory(hereinafter referred to as a set of the same-index entries), into oneof which the line to be accessed by the command is to be stored, anddetermines a line to be replaced by selecting out of the previouslystored lines in the set of the same-index entries, according to thestatus, LRU, and attribute information for the lines stored in the set(hereinafter referred to as lines stored in the set of the same-indexentries), the attribute (hereinafter referred to as group Gr to whichthe line to be stored belongs) of the line to be stored (hereinafterreferred to as line Lr to be stored) and the policy of storing.
 10. Thecache memory unit according to claim 9, wherein: said replace lineselector determines a line to be replaced as follows: among the lines L1, . . . , Ln stored in the set of the same-index entries, if lines Li, .. . , Lj put in invalid status (hereinafter referred to as Invalid)exist (this condition is hereinafter referred to as Condition 1), thereplace line selector selects a line to be replaced out of the lines Li,. . . , Lj (this action is hereinafter referred to as Action 1); amongthe lines L1 , . . . , Ln stored in the set of the same-index entries,if the number of the lines L (Gr) belonging to the group Gr to which theline to be stored belongs is equal to or greater than the number ofgroup sets P (Gr) comprising or including the group Gr member, definedin the policy of storing (L (Gr)≧P (Gr)) (this condition is hereinafterreferred to as Condition 2), the replace line selector selects a line tobe replaced out of the lines Lk, . . . , L1 belonging to the group Gr towhich the line to be stored belongs among those stored in the set of thesame-index entries, according to the LRU information (this action ishereinafter referred to as Action 2); among the groups (G1, . . . ,Gr−1, Gr+1, . . . , Gm) other than the group Gr to which the line to bestored belongs, if groups Gp, . . . , Gq exist that meet the conditionthat the number of the lines stored in the set of the same-index entriesand belonging to a particular group is greater than the number of themembers identified as this particular group included in said group sets(P (G1), . . . , P (Gr−1), P (Gr+1), . . . , P (Gm)) (L (Gp)>P (Gp), . .. , L (Gq)>P (Gq)) (this condition is hereinafter referred to asCondition 3), the replace line selector selects a line to be replacedout of the lines Ls, . . . , Lt belonging to any of the groups Gp, . . ., Gq, according to the LRU information (this action is hereinafterreferred to as Action 3); and if none of Condition 1, Condition 2, andCondition 3 are satisfied, the replace line selector targets lines Lv, .. . , Lw that belong to group Gu, a member joined one of said group setsthat also includes the group Gr member to which the line to be storedbelongs among the lines stored in the set of the same-index entries, andselects a line to be replaced out of the lines Lv, . . . Lw, accordingto the LRU information.
 11. The cache memory unit according to claim 10,wherein: said replace line selector executes Action 1 if the followingcondition, instead of Condition 1, is satisfied: among the lines L1, . .. , Ln stored in the set of the same-index entries, lines Li, . . . , Ljput in Invalid status exist; and among the lines L1, . . . , Ln storedin the set of the same-index entries, the number of the lines L (Gr)belonging to the group Gr to which the line to be stored belongs is lessthan the number of group sets P (Gr) comprising or including the groupGr member (L Gr)<P (Gr)).
 12. The cache memory unit according to claim11, wherein: as the policy of storing assigned by means of said policydefinition controller, as many grouping attributes as the number ofbanks n of the cache memory are predetermined with each attribute beingmapped to one of the cache memory banks; and said replace line selectorexecutes Action 1 if the following condition, instead of Condition 1, issatisfied: among the lines L1, . . . , Ln stored in the set of thesame-index entries, lines Li, . . . , Lj put in Invalid status exist;and group sets comprising or including the group Gr member to which theline to be stored belongs are mapped to the memory banks M (Li), . . . ,M (Lj) where the line Li, . . . , Lj are stored respectively; ifCondition 2 is satisfied, the replace line selector executes thefollowing action, instead of Action 2: the replace line selector selectsa line to be replaced out of lines Lo, . . . , Lp stored in the entrieson the memory banks to which the group sets Pk, . . . , P1 comprising orincluding the group Gr member to which the line to be stored belongs aremapped, according to the LRU information for the lines; and if Condition3 is satisfied, the replace line selector executes the following action,instead of Action 3: the replace line selector selects a line to bereplaced out of lines Ls, . . . , Lt belonging to any of the groups Gp,. . . , Gq and stored in the entries on the memory banks M (Ls) , . . ., M (Lt) to which the group sets comprising or including the Gr groupmember to which the line to be stored belongs are mapped, according tothe LRU information.
 13. A cache memory unit comprising: a partitiondefinition means that is used to specify what processor belongs to whatpartition for a plurality of processors grouped into a plurality ofpartitions; a group definition controller that is used to definegrouping of lines to be put under management for each partition definedby the partition definition means; a policy definition controller thatis used to set policy of storing whereby to store lines into thesame-index entries on the banks of the cache memory in one of thepatterns of combinations of groups, to any of which the lines belong,according to the grouping defined for the partition, for each partitiondefined by the partition definition means; and a plurality of memorycontrollers placed between said processors and a main memory andconnected to the processors and the main memory, each memory controllercomprising: 1) a plurality of cache memories to temporarily store datain units of lines of given size retrieved from the main memory in datablock units in the main memory and store control information associatedwith each line it retains; 2) a group selector to determine one of thegroups defined by means of said group definition controller as the groupto which a line to be fetched belongs, according to the information in acommand that has been issued from one of the processors connected tosaid memory controller to fetch a data block from said main memory; 3) ahit checker to judge whether a line specified to be read in the commandfrom one of the processors remains stored on the cache memory; 4) areplace line selector to determine a line to be replaced and removedfrom the cache memory in accordance with the group to which a new linebelongs, determined by said group selector, the line control informationretained in said cache memory for the candidate lines to be replaced,and the policy of storing set by means of said policy definitioncontroller if the judgment of said hit checker is a missed hit. 5) astoring means to retrieve said line specified to be read from the mainmemory and store the line with control information for the line in placeof the line determined to be replaced by said replace line selector intothe cache memory if the judgment of said hit checker is a missed hit.